<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW5A-25A" pn="GW5A-LV25UG324C2/I1">gw5a25a-008</Device>
    <FileList>
        <File path="src/clk_test_tb.v" type="file.verilog" enable="1"/>
        <File path="src/clock_test.v" type="file.verilog" enable="1"/>
        <File path="src/gowin_pll/gowin_pll.v" type="file.verilog" enable="1"/>
        <File path="src/test_acg525.cst" type="file.cst" enable="1"/>
        <File path="src/test_ACG525.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>
